(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, directed to a split-gate flash memory having an increased coupling ratio of source to floating gate and to a method of forming of the same.
(2) Description of the Related Art
The degree of coupling between a source and floating gate in a split-gate flash memory is determined by the capacity of source implant lateral diffusion under the floating gate. It is desirable to increase the coupling ratio because that results in improved programming speed. However, trying to increase coupling ratio by increasing the source implant lateral diffusion causes the well-known problems of punch-through and junction breakdown. It is disclosed later in the embodiments of this invention a method of increasing the coupling ratio of a split-gate memory cell by extending into the trench isolation region of the cell a three-dimensional source. Because of the additional vertical wall area in the third dimension, the coupling is increased, and the performance of the cell improved.
A conventional split-gate flash memory device is characterized by its split-gate side (between the control gate and the drain) and the stacked-side (between the floating gate and the source) and by a coupling ratio between the floating gate and the source. As is known, the coupling ratio affects the program speed, that is, the larger the coupling ratio, the faster is the programming speed, and is not a fixed value by virtue of the variability of the channel length and hence that of the overlap between the floating gate and the source. Usually, if channel length is increased through greater lateral diffusion in the source region, punchthrough occurs due to excessive current well below the threshold voltage. It is shown in the present invention that the coupling ratio can be increased without increasing the channel length, but by incorporating side-wall coupling of the vertical wall in a three-dimensional source, thus alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. Here, two MOS transistors share a source (25). Each transistor is formed on a semiconductor substrate (10) having a first doped region (20), a second doped region (25), a channel region (23), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (23) have a first conductivity type, and the first (20) and second (25) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (20), lies within the substrate. The second doped region, (25), also lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (23) lies within substrate (10) and between first (20) and second (25) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
In the structure shown in FIG. 1, control gate (60) overlaps the channel region, (23 under the floating gate, (40). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (23) determines the cell performance. Furthermore, edges (41), (43) can affect the programming of the cell by the source size and hot electron injection through the intergate dielectric layer (50) at such edges. Hot electron injection is further affected by, what is called, gate bird's beak (43) that is formed in conventional cells. On the other hand, it will be known to those skilled in the art that corners such as (41) can affect the source coupling ratio also. Any such adverse effects attributable source size can be alleviated as disclosed later in the embodiments of this invention.
To program the transistor shown in FIG. 1, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed "on" of "off." "Reading" of the cell's state is accomplished by applying appropriate voltages to the cell source (25) and drain (20), and to control gate (60), and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate.
In the conventional memory cell shown in FIG. 1, word lines (not shown) are connected to control gate (60) of the MOS transistor, while the length of the MOS transistor itself is defined by the source (25) drain (20) n+ regions shown in the same Figure. As is well known by those skilled in the art, the transistor channel is defined by masking the n+ regions. However, the channel length of the transistor varies depending upon the alignment of the floating gate (40) with the source and drain regions. This introduces significant variations in cell performance from die to die and from wafer to wafer. Furthermore, the uncertainty in the final position of the n+ regions causes variations in the series resistance of the bit lines connected to those regions, and hence additional variation in the cell performance.
In prior art, different methods for fabricating different split-gate memory cells are taught. In U.S. Pat. No. 5,495,441, Hong discloses a split-gate flash memory cell having a vertical isolation gate and a process for making it. The memory cell has a floating gate transistor formed in a substrate having a channel extending underneath a floating gate, and a vertical isolation transistor formed in the substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate. In another U.S. Pat. No. 5,414,287, Hong teaches a process for high density split-gate memory cell for flash or EPROM. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer surround the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over a portion of the vertical surfaces of the first dielectric layer, and acts as a floating gate for the high density split-gate memory cell. A source region is located in the silicon substrate. A drain region is located in the top of the silicon islands. A second dielectric layer is formed over the top and side surfaces of the floating gate, and acts as an interpoly dielectric. A second conductive layer is formed over that remaining portion of the vertical surfaces of the first dielectric layer not covered by the first conductive layer, and surrounds the second dielectric layer, whereby the second conductive layer is a control gate.
A different process for trench-isolated self-aligned split-gate EEPROM transistor and memory array is described by Hazani in U.S. Pat. No. 5,162,247. A still different method of manufacturing an EEPROM with trench-isolated bitlines is taught by Gill, et al., in U.S. Pat. No. 5,173,436. Here, an EEPROM cell is constructed using a floating-gate transistor with or without a split gate. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in a tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.
In the present invention, a method to increase the coupling ratio of source to floating gate is disclosed without increasing lateral diffusion under the floating gate. This prevents punch-through and junction breakdown problems. The increase in coupling ratio is accomplished by providing a three-dimensional source extending into trench isolation, whereby the vertical wall in the third dimension provides the extra area through which coupling between the source and the floating gate is also increased. It will be appreciated by those skilled in the art that in this manner a higher coupling ratio is achieved without an increase in the cell size.